“PCB (Printed Circuit Board) wiring plays a key role in high-speed circuits. This article mainly discusses the wiring of high-speed circuits from a practical perspective. The main purpose is to help new users pay attention to many different issues that need to be considered when designing high-speed circuit PCB layouts.
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PCB (Printed Circuit Board) wiring plays a key role in high-speed circuits. This article mainly discusses the wiring of high-speed circuits from a practical perspective. The main purpose is to help new users pay attention to many different issues that need to be considered when designing high-speed circuit PCB layouts.
Another purpose is to provide a review material for customers who have not touched PCB wiring for a while. Due to the limited space, this article cannot discuss all the issues in detail, but we will discuss the key parts that have the greatest effect on improving circuit performance, shortening design time, and saving modification time.
Although this is mainly for circuits related to high-speed operational amplifiers, the problems and methods discussed here are generally applicable to wiring used in most other high-speed analog circuits. When the operational amplifier works in a very high radio frequency (RF) frequency band, the performance of the circuit largely depends on the PCB layout.
High-performance circuit designs that look good on the “drawings” can only get ordinary performance if they are affected by careless wiring. Pre-consideration and attention to important details during the entire wiring process will help ensure the expected circuit performance.
Schematic
Although a good schematic cannot guarantee a good wiring, a good wiring starts with a good schematic. Think carefully when drawing the schematic, and you must consider the signal flow of the entire circuit. If there is a normal and stable signal flow from left to right in the schematic, then there should be an equally good signal flow on the PCB.
Give as much useful information as possible on the schematic. Because sometimes the circuit design engineer is not there, customers will ask us to help solve the circuit problem, the designers, technicians and engineers engaged in this work will be very grateful, including us.
In addition to the common reference identifier, power consumption, and error tolerance, what information should be given in the schematic? Here are some suggestions to turn a common schematic into a first-class schematic. Add waveforms, mechanical information about the casing, length of printed lines, blank areas; indicate which components need to be placed on the PCB; give adjustment information, component value ranges, heat dissipation information, control impedance printed lines, comments, and brief circuits Action description… (and others)
Don’t believe anyone
If you are not designing the wiring yourself, be sure to allow plenty of time to carefully check the wiring person’s design. At this point, a small prevention is worth a hundred times the remedy. Don’t expect the wiring person to understand what you think. In the early stages of the wiring design process, your opinions and guidance are the most important. The more information you can provide, and the more you intervene in the entire wiring process, the better the resulting PCB will be.
Set a tentative completion point for the wiring design engineer-quick check according to the wiring progress report you want. This “closed loop” method prevents the wiring from going astray, thereby minimizing the possibility of rework.
The instructions that need to be given to the wiring engineer include: a short description of the circuit function, a PCB schematic drawing indicating the input and output locations, PCB stacking information (for example, how thick the board is, how many layers there are, and detailed information about each signal layer and ground plane-function Power consumption, ground wire, analog signal, digital signal and RF signal); which signals are required for each layer; require the placement of important components;
The exact location of the bypass components; which printed lines are important; which lines need to control the impedance printed lines; which lines need to be matched in length; the size of the components; which printed lines need to be far away (or close to) each other; which lines need to be far away from each other (Or close); which components need to be far away from each other (or close); which components should be placed on the top of the PCB and which should be placed below. Never complain that there is too much information for others-too little? Yes; too much? No.
A learning experience:
About 10 years ago, I designed a multi-layer surface mount circuit board-there are components on both sides of the board. Use a lot of screws to fix the board in a gold-plated aluminum shell (because there are very strict anti-vibration indicators). The pins that provide bias feedthrough pass through the board. This pin is connected to the PCB by soldering wires. This is a very complicated device. Some components on the board are used for test setting (SAT). But I have clearly defined the location of these components. Can you guess where these components are installed? By the way, under the board. When product engineers and technicians had to disassemble the entire device and reassemble them after completing the settings, they seemed very unhappy. I haven’t made this mistake again since then.
Location
Just like in a PCB, location is everything. Where to put a circuit on the PCB, where to install its specific circuit components, and what other adjacent circuits are, all of which are very important.
Usually the positions of input, output and power supply are predetermined, but the circuit between them needs to “play their own creativity.” This is why paying attention to wiring details will yield huge rewards. Start with the location of key components and consider the specific circuit and the entire PCB.
Specifying the location of key components and signal paths from the beginning helps to ensure that the design meets the expected work goals. Getting the right design the first time can reduce costs and pressure-and shorten the development cycle.
Bypass power
Bypassing the power supply at the power supply side of the amplifier in order to reduce noise is a very important aspect in the PCB design process-including high-speed operational amplifiers or other high-speed circuits. There are two common configuration methods for bypassing high-speed operational amplifiers.
Grounding the power terminal:
This method is the most effective in most cases, using multiple capacitors in parallel to connect the power supply pins of the op amp directly to ground. Generally speaking, two parallel capacitors are sufficient-but adding parallel capacitors may bring benefits to some circuits.
Parallel connection of capacitors with different capacitance values helps to ensure that only a very low alternating current (AC) impedance can be seen on the power supply pin over a wide frequency band. This is especially important at the attenuation frequency of the operational amplifier power supply rejection ratio (PSR). This capacitor helps compensate for the reduced PSR of the amplifier.
Maintaining a low-impedance ground path in many ten-octave ranges will help ensure that harmful noise cannot enter the op amp. Figure 1 shows the advantages of using multiple capacitors in parallel. At low frequencies, large capacitors provide a low impedance ground path. But once the frequency reaches their own resonant frequency,
The capacitance of the capacitor will be weakened and gradually appear inductive. This is why it is important to use multiple capacitors: when the frequency response of one capacitor starts to drop, the frequency response of the other capacitor starts to work, so it can maintain a very low AC impedance in many ten-octave ranges.
Figure 1. The relationship between the impedance of a capacitor and frequency
Start directly from the power supply pin of the operational amplifier; the capacitor with the smallest capacitance value and the smallest physical size should be placed on the same side of the PCB as the operational amplifier-and as close as possible to the amplifier. The ground terminal of the capacitor should be directly connected to the ground plane with the shortest pin or printed wire. The above ground connection should be as close as possible to the load end of the amplifier in order to reduce the interference between the power supply end and the ground end. Figure 2 shows this connection method.
Figure 2. Parallel capacitor bypassing power supply terminal and ground
This process should be repeated for capacitors with the next largest capacitance value. It is best to start with the minimum capacitance value of 0.01 µF and place a 2.2 µF (or larger) electrolytic capacitor with low equivalent series resistance (ESR) close to it. It adopts a 0.01 µF capacitor with a 0508 case size, which has very low series inductance and excellent high frequency performance.
Power end to power end:
Another configuration method uses one or more bypass capacitors connected across the positive power supply terminal and the negative power supply terminal of the operational amplifier. This method is usually used when it is difficult to configure four capacitors in the circuit. Its disadvantage is that the size of the capacitor’s case may increase because the voltage across the capacitor is twice the value of the voltage in the single-supply bypass method. Increasing the voltage requires increasing the rated breakdown voltage of the device, that is, increasing the size of the case. However, this method can improve PSR and distortion performance.
Parasitic effect
Because each circuit and wiring is different, the configuration, number and capacitance value of capacitors should be determined according to the requirements of the actual circuit.
The so-called parasitic effects are those small faults (literally) that sneak into your PCB and cause great damage in the circuit, headaches, and unexplained causes. They are the parasitic capacitance and parasitic inductance that penetrate into the high-speed circuit.
Including the parasitic inductance formed by the package pin and the printed line is too long; the parasitic capacitance formed between the pad to the ground, the pad to the power plane and the pad to the printed line; the mutual influence between the vias, and Many other possible parasitic effects. Figure 3 (a) shows a typical schematic diagram of a non-inverting operational amplifier.
However, if you consider the parasitic effects, the same circuit may become like Figure 3 (b).
Figure 3. A typical operational amplifier circuit, (a) the original design diagram, (b) the diagram after considering the parasitic effects
In high-speed circuits, a small value will affect the performance of the circuit. Sometimes dozens of picofarads (pF) are sufficient. Related example: If there is only 1 pF of additional parasitic capacitance at the inverting input, it can cause almost 2 dB spikes in the frequency domain (see Figure 4). If the parasitic capacitance is large enough, it will cause instability and oscillation of the circuit.
Figure 4. Additional spikes caused by parasitic capacitance
When looking for problematic parasitic sources, several basic formulas for calculating the size of the parasitic capacitances mentioned above may be used. Formula (1) is the formula for calculating parallel plate capacitors (see Figure 5).
C represents the capacitance value, A represents the plate area in cm2, k represents the relative permittivity of the PCB material, and d represents the distance between the plates in cm.
Figure 5. Capacitance between two plates
Strip inductance is another parasitic effect that needs to be considered. It is caused by too long printed lines or lack of ground planes. The formula (2) shows the formula for calculating the inductance of the printed line (Inductance). See Figure 6.
W represents the width of the printed line, L represents the length of the printed line, and H represents the thickness of the printed line. All dimensions are in mm.
Figure 6. Printed line inductance
The oscillation in Figure 7 shows the effect of the 2.54 cm printed line at the non-inverting input of the high-speed operational amplifier. Its equivalent parasitic inductance is 29 nH (10-9H), which is enough to cause continuous low-voltage oscillation, which will continue throughout the transient response period. Figure 7 also shows how to use the ground plane to reduce the impact of parasitic inductance.
Figure 7. Impulse response with and without ground plane
Vias are another parasitic source; they can cause parasitic inductance and parasitic capacitance. Formula (3) is the formula for calculating parasitic inductance (see Figure 8).
T represents the thickness of the PCB, and d represents the diameter of the through hole in cm.
Figure 8. Through hole dimensions
Equation (4) shows how to calculate the parasitic capacitance caused by the via (see Figure 8).
εr represents the relative permeability of the PCB material. T represents the thickness of the PCB. D1 represents the diameter of the land surrounding the through hole. D2 represents the diameter of the isolation hole in the ground plane. All dimensions are in cm. A through hole on a 0.157 cm thick PCB can increase the parasitic inductance of 1.2 nH and the parasitic capacitance of 0.5 pF; this is why it is necessary to keep alert when wiring the PCB to reduce the influence of parasitic effects The smallest.
Ground plane
In fact, the content that needs to be discussed is far more than those mentioned in this article, but we will highlight some key features and encourage readers to further explore this topic. Related references are listed at the end of this article.
The ground plane acts as a common reference voltage, provides shielding, can dissipate heat and reduce parasitic inductance (but it also increases parasitic capacitance). Although there are many benefits to using a ground plane, care must be taken when implementing it, because it has some restrictions on what can and cannot be done.
Ideally, one layer of the PCB should be dedicated as a ground plane. This will produce the best results when the entire plane is not destroyed. Never misappropriate the area of the ground plane in this dedicated layer to connect to other signals. Since the ground plane can eliminate the magnetic field between the conductor and the ground plane, the printed line inductance can be reduced. If a certain area of the ground plane is destroyed, unexpected parasitic inductance will be introduced to the printed lines above or below the ground plane.
Because the ground plane usually has a large surface area and cross-sectional area, keep the resistance of the ground plane to a minimum. In the low frequency band, the current will choose the path with the least resistance, but in the high frequency band, the current will choose the path with the least impedance.
However, there are exceptions, and sometimes a small ground plane is better. If the ground plane is moved away from the input or output pads, the high-speed operational amplifier will work better. Because of the parasitic capacitance introduced at the ground plane of the input end, the input capacitance of the operational amplifier is increased, and the phase margin is reduced, thereby causing instability. As seen in the discussion of parasitic effects, a 1 pF capacitor at the input of an op amp can cause significant spikes. Capacitive loads on the output-including parasitic capacitive loads-cause poles in the feedback loop. This reduces the phase margin and causes the circuit to become unstable.
If possible, analog circuits and digital circuits—including their respective ground and ground planes—should be separated. A fast rising edge can cause current glitches to flow into the ground plane. The noise caused by these fast current spikes can ruin the analog performance. The analog ground and digital ground (and power supply) should be connected to a common ground point to reduce circulating digital and analog ground currents and noise.
In the high frequency range, a phenomenon called “skin effect” must be considered. The skin effect causes current to flow on the outer surface of the wire-as a result, the cross-section of the wire becomes narrower, thereby increasing the direct current (DC) resistance. Although the skin effect is beyond the scope of this article, here is a good approximate formula (in cm) for the skin depth (Skin Depth) in the copper wire:
Low-sensitivity electroplated metal helps reduce skin effect
Encapsulation
Operational amplifiers usually adopt different packages. The selected package will affect the high frequency performance of the amplifier. The main effects include parasitics (mentioned earlier) and signal paths. Here we focus on the path input, output and power supply of the amplifier.
Figure 9 shows the wiring difference between the SOIC package (a) and the SOT-23 package (b). Each package has its own problems. Focus on (a). If you carefully observe the feedback path, you will find that there are multiple ways to connect feedback. The most important thing is to ensure that the length of the printed line is the shortest. Parasitic inductance in the feedback path can cause ringing and overshoot. In Figures 9(a) and 9(b), the feedback path is connected around the amplifier.
Figure 9(c) shows another method—connecting the feedback path under the SOIC package—which reduces the length of the feedback path. Each method has subtle differences. The first method will cause the printed line to be too long and increase the series inductance. The second method uses through holes, which will cause parasitic capacitance and parasitic inductance. The influence of these parasitic effects and their hidden problems must be considered when wiring the PCB.
SOT-23 wiring difference is almost ideal: the feedback trace length is the shortest, and through holes are rarely used; the load and bypass capacitors return from a short path to the same ground connection; the capacitor on the positive power supply terminal (Figure 9 (b) Not shown) Place it directly below the negative power supply capacitor on the back of the PCB.
Figure 9. The wiring difference of the same operational amplifier circuit. (a) SOIC package, (b) SOT-23 package, (c) SOIC package with RF under the PCB
Pinout of low-distortion amplifier: Some operational amplifiers provided by ADI (such as AD80451) use a new low-distortion pinout to help eliminate the two problems mentioned above; and it also improves the other two An important aspect of performance. The low distortion pin arrangement of LFCSP, as shown in Figure 10, moves the pin arrangement of the traditional operational amplifier counterclockwise by one pin and adds an output pin as a dedicated feedback pin.
Figure 10. Operational amplifier with low distortion pinout
The low distortion pin arrangement allows close connections between the output pin (dedicated feedback pin) and the inverting input pin, as shown in Figure 11. This greatly simplifies and improves the wiring.
Figure 11. PCB layout of AD8045 low distortion operational amplifier
Another advantage of this pin arrangement is that it reduces the second harmonic distortion. One reason for the second harmonic distortion in the pin configuration of the traditional operational amplifier is the coupling between the non-inverting input and the negative power supply pin. The low-distortion pin arrangement of the LFCSP package eliminates this coupling so that the second harmonic distortion is greatly reduced; in some cases, it can be reduced by up to 14 dB. Figure 12 shows the difference in distortion performance between AD80992 in SOIC package and LFCSP package.
This kind of packaging has another advantage-low power consumption. The LFCSP package has an exposed pad, which reduces the thermal resistance of the package, thereby improving the θJA value by about 40%. Because the thermal resistance is reduced, the operating temperature of the device is reduced, which is equivalent to improving reliability.
Figure 12. AD8099 different package distortion performance comparison-the same operational amplifier is packaged in SOIC and LFCSP
Wiring and shielding
There are a variety of analog and digital signals on the PCB, including high to low voltage or current, from DC to GHz frequency range. It is very difficult to ensure that these signals do not interfere with each other.
Looking back at the suggestions in the “Don’t Believe Nobody” section above, the most important thing is to think in advance and make a plan for how to deal with the signals on the PCB. It is important to pay attention to which signals are sensitive and determine what measures must be taken to ensure signal integrity. The ground plane provides a common reference point for electrical signals and can also be used for shielding. If signal isolation is required, a physical distance should be left between the signal traces. Here are some practical experiences worth learning:
Reducing the length of the long parallel wires in the same PCB and the proximity between the signal printed wires can reduce inductive coupling.
Reducing the length of long traces in adjacent layers can prevent capacitive coupling.
Signal traces that require high isolation should go on different layers and-if they are not completely isolated-they should go on orthogonal traces, and the ground plane should be placed between them. Orthogonal wiring minimizes capacitive coupling, and the ground wire forms an electrical shield. This method can be used when forming a controlled impedance printed line.
High frequency (RF) signals usually flow on control impedance traces. That is, the printed line maintains a characteristic impedance, such as 50Ω (a typical value in RF applications). The two most common controlled impedance printed lines, the microstrip line 4 and the strip line 5 can achieve similar effects, but the implementation methods are different.
The microstrip controlled impedance printed line, as shown in Figure 13, can be used on any side of the PCB; it directly uses the ground plane below it as its reference plane.
Figure 13. Microstrip transmission line
Equation (6) can be used to calculate the characteristic impedance of an FR4 board.
H represents the distance from the ground plane to the signal trace, W represents the width of the trace, and T represents the thickness of the trace; all dimensions are in mils (10-3 inches). εr represents the dielectric constant of the PCB material.
The strip control impedance printed line (see Figure 14) uses a two-layer ground plane, and the signal printed line is clamped in it. This method uses more printed lines, requires more PCB layers, is sensitive to changes in dielectric thickness, and is more costly-so it is usually only used in demanding applications.
Figure 14. Ribbon control impedance printed line
The formula for calculating the characteristic impedance of the stripline is shown in formula (7).
The guard ring, or “isolation ring”, is another shielding method commonly used in operational amplifiers to prevent parasitic currents from entering sensitive nodes. The basic principle is very simple-use a protective wire to completely surround the sensitive node, and the wire maintains or forces it to maintain (low impedance) the same potential as the sensitive node, so that the absorbed parasitic current is far away from the sensitive node.
Figure 15(a) shows a schematic diagram of the guard ring used in the inverting configuration and the non-inverting configuration of the operational amplifier. Figure 15(b) shows a typical wiring method for the two guard rings in the SOT-23-5 package.
Figure 15. Guard ring. (a) Reverse and in-phase operation. (b) SOT-23-5 package
High-level PCB wiring is very important for successful operational amplifier circuit design, especially for high-speed circuits. A good schematic diagram is the basis of good wiring; close cooperation between circuit design engineers and wiring design engineers is fundamental, especially with regard to the location of components and wiring. Issues that need to be considered include bypassing the power supply, reducing parasitic effects, using ground planes, the impact of op amp packaging, and wiring and shielding methods.
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