“The attitude computer in the strapdown inertial navigation realizes the digital platform navigation, which needs to be able to complete the acquisition of various sensor measurement data and the transmission of the attitude results and system status at a high speed and accurately while performing complex operations. The usual practice is to use one or more DSP chips to complete, but when there are many data interfaces and the data transmission frequency is high, the real-time performance of such systems is difficult to be guaranteed; Realize multi-module parallel work, and can achieve higher operating frequency.
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The attitude computer in the strapdown inertial navigation realizes the digital platform navigation, which needs to be able to complete the acquisition of various sensor measurement data and the transmission of the attitude results and system status at a high speed and accurately while performing complex operations. The usual practice is to use one or more DSP chips to complete, but when there are many data interfaces and the data transmission frequency is high, the real-time performance of such systems is difficult to be guaranteed; Realize multi-module parallel work, and can achieve higher operating frequency. In addition, using FPGA to design the attitude computer also has the following outstanding advantages: low cost, low power consumption, small size, reprogrammability, easy upgrade, reusable VHDL design circuit, etc. This paper introduces in detail how to design FPGA in the heading and attitude computer with many interfaces, so that various communication interface functions can be realized in real time and reliably, which has practical engineering significance.
1. Overall system design
Figure 1 is a block diagram of the hardware structure of the strapdown attitude system. The system needs to collect measurement data of various sensors (including atmospheric sensors, IMU, magnetic compass) and some related analog quantities at high speed and in real time, which are used for high-precision heading and attitude calculation in DSP. And system information is sent to multiple devices (including flight parameter recorder, Display instrument and DS). The interfaces that need to be used at the same time to collect data include ARINC429, RS422, SPI, parallel interface with DSP and other interfaces; the completion of such a large number and variety of interfaces must also ensure accuracy and real-time performance. The timing and logic control of the entire system are completed by FPGA, and DSP (select TMS320C6713 from TI) is used as a slave processor for the attitude calculation. The FPGA chip selected in this system is the APA300 chip in the PA series of ACTEL Company, which is developed in the LibroIDE environment with VHDL language.
2. FPGA implementation of various industrial interfaces
(1) RS422 communication interface. The RS422 standard is a communication standard that uses differential transmission to improve communication distance and reliability. The attitude computer needs to use RS422 interface to communicate with six external devices such as IMU, atmospheric sensor, magnetic compass, and radio air watch. Since RS422 can support duplex working mode, in order to make full use of resources, four identical parallel interface modules are designed, each of which is realized by controlling the MAX3140 chip through FPAG (as shown in Figure 2); Considering the design efficiency, only one general entity is designed, and each control module is used as an instance of this entity. In this way, although the structure of these four modules is exactly the same, the two simplex and two duplex working modes are realized by applying different controls in the top-level entity. According to the working sequence diagram of MAX3140, this general entity completes the on-chip by controlling and monitoring five pins of UART (SCLK data receiving clock, CS chip select signal, DIN control data input, IRQ interrupt, DOUT data output). Electrical self-checking and receiving and sending of signals; the top-level entity controls the work of the four entities in parallel, thereby realizing the receiving and sending of the above-mentioned multi-channel signals without affecting each other.
(2) ARINC429 communication interface. The ARINC429 protocol specifies the digital data transmission standard between the aviation transportation industry, avionics systems and other systems, and is an important interface in the Electronic communication of avionics systems. The system needs to receive the measurement data of the main inertial navigation through the ARINC429 interface, and at the same time send the flight parameters to the recorder through the ARINC429 interface. Due to the requirements of communication reliability, the control interface chip is also used in this design. 8585 chip combination. The chip also supports duplex mode. According to the working sequence diagram of HI-3584 in FPGA, a series of parallel processes are designed to control and monitor the reset signal of HI-3584, send and receive clock signals, read and write control signals and 16-bit data signals (as shown in Figure 3). ). In this way, the power-on self-test of the HI-3582, the reception of a channel 429 signal and the transmission of a channel 429 signal are completed.
(3) SPI interface. The SPI interface is a high-speed, serial, full-duplex, synchronous transmission method. Generally, it is realized by a master device and one or more slave devices through five pins such as interrupt, clock, input data, output data and chip select signal. This design needs to use AD sampling chip to collect analog quantity, and the selected AD chip communicates with FPGA in SPI mode. The AD sampling chip is the TLV2548 chip of TI Company, with 8 channels, 12 bits, and a sampling frequency of 200ksps. According to the working sequence diagram of TLV2548 in FPGA, a series of parallel processes are designed to control and monitor the interrupt signal, receive clock signal, chip select signal, data input signal and data output signal of TLV2548 (as shown in Figure 4). In this way, the acquisition of 8 channels of analog quantity is completed. In this design, an external reference was initially selected, and it was found that the precision adjustable resistor used for voltage division would change the resistance value with time, which would seriously affect the accuracy. Therefore, the internal reference was finally used to truly ensure the reliability of the analog quantity. In addition, the used internal crystal oscillator provides high-frequency sampling, so that the data update rate is higher than 1M, thus ensuring the real-time performance of the data.
(4) Parallel interface with DSP. The parallel interface is one of the most commonly used communication methods. The data communication between FPGA and DSP is completed through a 16-bit parallel interface (the schematic diagram is shown in Figure 5). First of all, according to the timing of the DSP, the DSP needs to be reset for no less than 200ms after the system is powered on. During the normal working period of the system, when WE=0 is valid for writing, CE1=0 is valid for chip selection, and a21=1 is valid for data, FPGA reads DSP data from the bus, and when OE=0 is valid for reading, CE1=0 is valid for chip selection , a21=1 When the data is valid, the FPGA puts the data on the bus and waits for the DSP to read it. The FPGA reads and writes data according to the EA signal of the DSP to identify the operated data address. Although the amount of data in the system is relatively large, in order to improve real-time and reliability, FIFO or RAM is not used to store data in FPGA, but only variables in FPGA are used for temporary storage. This design also finally proves the design Availability, so that the hardware resources of the FPGA can be used more reasonably.
3. Implementation of the overall timing
The real-time nature and complexity of this system pose a great challenge to the correct realization of the overall timing and working logic. The implementation method of this design is described from the following aspects:
1 High-speed real-time performance: The overall parallel design, each communication module works almost completely independently, and does not occupy resources for each other, so that the requirements of high efficiency and real-time performance have been greatly satisfied.
2. Overall sequence order: The overall sequence and overall logic of the heading and attitude computer are controlled by the top-level entity in the FPGA. The general sequence and logic of the system are as follows: after power-on, after the FPGA control system completes the power-on self-test of each component, each interface starts to work in parallel, and receives and sends data according to its own working sequence. Among them, the IMU data is sent about every 10ms, and the FPGA communicates with the DSP through a parallel interface after receiving the IMU data each time. The FPGA sends the latest sensor measurement value to the DSP, and the DSP sends the latest heading information back to the FPGA, and finally the FPGA transmits it to the outside through the ARINC429 interface. Such a design ensures that the system timing sequence is stable and the logic is reliable.
3 Data Accuracy: Data accuracy also requires consideration of specific hardware issues. Since the logic gates in the FPGA have time delays, in such a real-time system, the delay of the gate circuits must be strictly considered. Otherwise, the following similar problems are prone to occur. It takes a few nanoseconds to a dozen nanoseconds to stabilize a variable. If it happens to be triggered by the clock that operates the change variable, it will occasionally cause outlier data. These uncertain outliers may cause the entire navigation at any time. Therefore, it needs to be modified according to the specific timing to ensure that such problems are eliminated.
The FPGA design of the system has been verified by the simulation data simulation test and the sports car test, and has been well satisfied in terms of data accuracy and real-time performance.
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