“Signal integrity is one of the main topics that many designers deal with in the design of high-speed digital circuits. Signal integrity involves quality degradation and timing errors in digital signal waveforms as the signal travels from the transmitter to the receiver through interconnect paths such as package structures, PCB traces, vias, flex cables, and connectors.
Signal integrity is one of the main topics that many designers deal with in the design of high-speed digital circuits. Signal integrity involves quality degradation and timing errors in digital signal waveforms as the signal travels from the transmitter to the receiver through interconnect paths such as package structures, PCB traces, vias, flex cables, and connectors.
Today’s high-speed bus designs such as LpDDR4x, USB 3.2 Gen1/2 (5Gbps/10Gbps), USB3.2×2 (2x10Gbps), PCIe and the upcoming USB4.0 (2x20Gbps) when high frequency data flows from transmitter to receiver Signal attenuation will occur. This article will provide an overview of signal integrity fundamentals and key issues such as skin effect, impedance matching, characteristic impedance, reflections, etc. for high-speed data rate systems.
As the silicon node adopts 10nm, 7nm and even 5nm processes, this enables high levels of integration and increased functionality at a given die size. In mobile applications, the trend is for higher frequencies and higher data rates, and to reduce operating core voltages such as 0.9v, 0.8V, 0.56V and even lower to optimize power consumption.
Operating at a higher frequency at a lower operating voltage results in a smaller threshold level or data valid window for a given bit of data, affecting trace and power plane power distribution and “eye diagram” closure.
Eye closure, caused by higher frequencies and lower operating voltages, increases the chance of data transmission errors, and therefore bit error rates, which necessitate retransmission of the data stream. Retransmissions cause the processor to be in active mode for longer periods of time to retransmit the data stream, which results in higher power consumption and fewer days of use (DOU) for mobile applications.
Figure 1. Effect of Frequency and Lower Voltage on Eye Opening
When adding other design challenges such as signal attenuation, reflections, impedance matching, jitter, etc. to a given high frequency design, it becomes apparent that signal loss makes it difficult for the receiver to interpret the information correctly, thereby increasing the chance of error.
Clock Sampling in Data Stream
At the receiver, data is sampled at the edge of the reference clock. The larger the eye opening, the easier it is to set the sample CLK in the middle of a given bit to sample data. Any amplitude attenuation, reflections, or any jitter will make the eye more closed and the data valid window and valid bit time narrower, causing errors at the receiver.
Figure 2. CLK sampling
Now, let’s examine when a channel or interconnect needs to be considered a transmission line and look at some of the main reasons for transmission loss in systems like smartphones or tablets.
High Frequency and Transmission Lines
A low frequency design is one where the wavelength is much larger than the wire length and the resistance of the PCB traces and interconnects is independent of frequency, so the effect of the transmission line is negligible. High frequency design is when the wavelength is much smaller than the wire length and all physical properties of the trace and interconnect dimensions need to be controlled so that a transmission line with a range of electrical properties can be used for a given application.
When we think of an interconnect as a transmission line, it is operating at the highest frequency, where the trace length may exceed 1/10 of the wavelength at that frequency. At this point, we need to model the traces with lumped elements and take into account all frequency dependent components, including parasitic capacitance and inductance and their effect on signal attenuation.
Another way to determine at what frequency an interconnect is considered a transmission line is to consider the rise time (tr) of the signal.
In most nanometer process nodes, high data rate signals have sharp rise/fall times, which requires treating the channel or any interconnect as a transmission line. As these signals propagate through the channel, their bandwidth and transmission are governed by a given signal rise time.
Electrical signals are electromagnetic waves, the speed of which depends on the dielectric constant of the material around them.The formula for transfer speed is
Figure 3. Wave speed on a transmission line
The wave speed for lossless transmission in free space (dielectric constant 1) is about 3 x 108 m/s, unlike that of a transmission line with a dielectric constant of 4, which results in a wave speed reduction of half or 1.5 x 108 m/s. Differences in wave speeds traveling in free space versus traveling on a PCB will result in a time delay called propagation delay (Td), which depends on the medium of propagation and the distance the signal must travel.
Td (Propagation Delay) = Propagation Distance / Vp (Transmission Speed)
Now, what if we have free space on one side and permittivity on the other when one signal (CLK) propagates on the outer layer and another signal (Data) propagates on the inner layer?
In many designs, high-frequency signals must be part of the transmission path with interconnecting or flex cables, which can introduce delays and skew in amplitude and timing waveforms. Timing deviations or any other losses due to reduced signal speed, crosstalk, or any energy absorbed by the dielectric material will simultaneously produce timing and amplitude deviations called jitter.
Figure 4. Jitter
Here, the designer must match the time-of-flight between a series of signals. Since the DATA signal of the inner layer will propagate slower, we must reduce the length of the DATA signal to match the flight time of the CLK signal.
If we look at a section of a given conductor called C1 and send a current I
Figure 5. Current redistribution due to adhesion effects
As frequency increases, the skin effect confines the current to a smaller fraction of the conductor thickness, increasing the effective resistance and corresponding losses.
Figure 6. Signal Loss Due to Frequency and Trace Path
Transmission line and characteristic impedance Zo
The voltage and current on the transmission line propagate together and are a function of location (x) and time
Figure 7. Voltage and Current in Transmission Line
When the voltage V(x,t) and the current I(x,t) propagate together and reach the termination impedance, Ohm’s law requires that V(x,t)/I(x,t) equal the termination impedance (ZL).
Figure 8. Matching Zo and ZL
Impedance changes when a high frequency signal travels through a path in a PCB, passing through or changing its path from one layer to another. Looking at a given PCB, we can see that there are many layers, traces, vias, connections, impedances changing at any given point, and parasitic effects from self-capacitance, mutual capacitance, self-inductance, and mutual inductance.
Figure 9. PCB Layers and Impedance Variation
Now, let’s introduce some lumped elements like parasitic inductance, capacitance, AC skin resistance, DC resistance, which are present in any system. It can be seen how, for example, the parasitic capacitance (Cdx) changes the current distribution, which causes the characteristic impedance of the transmission line to change, and causes the Zo (transmission voltage to transmission current ratio) to change.
Figure 10. Transmission Line with Lumped Elements
As the skin effect reduces the amplitude of the incoming signal, the voltage across the parasitic inductance reduces the rise and fall times of the voltage across the load, affecting signal quality and attenuating the signal.
Figure 11. Parasitic Effects on Zo and Signal Integrity
voltage reflection coefficient
Impedance changes when high frequency signals pass through different paths, vias, or change their path from one layer to another. Controlling these spurious signals and properly terminating the transmission line, we can transmit the signal with minimal distortion.
When the termination impedance (ZL) is not equal to the characteristic impedance (Zo) of the line, there must be a pair of reflected voltage and current waves, and this reflected signal will overlay the source signal, causing distortion.
Note that the voltage reflection coefficient is equal to zero when the load termination (ZL) is equal to the characteristic impedance (Zo) of the transmission line. This indicates that all incident waves are absorbed by the matched load terminals.
When the voltage and current waves propagate together and reach the termination impedance, the total incident wave plus any reflected waves from V/I must equal the termination impedance (ZL).
Figure 12. Incident and reflected waves
Impedance mismatch and reflections
Consider a 50 ohm transmission line terminated with 150 ohm termination resistors or an overdamped circuit. For simplicity, we set the impedance of the battery to 0, which forces the reflected wave back to the load. Also, set the time delay (td = distance/Vp) for the wave to propagate for a given length. Now, let’s close the switch(s) and see what happens to the load.
Continuous reflected waves back and forth between the source and termination impedances can cause the signal to overlay the source signal and cause ringing on the signal line.
Figure 14. Ringing due to reflections
When calculating the reflection coefficients for the terminal and the source, we can derive the amount of incident wave reaching the terminal plus the amount of reflected wave reflected back to the source. The overshoot ringing in Figure 14 with a larger voltage will overstress the device by applying more radiation and create more crosstalk between adjacent traces. On the other hand, undershoot caused by ringing or a drop in the voltage rail during transient response will all add to a higher bit error rate.
Systems with and without redrivers
For some mobile applications, such as those using USB 3.1 Gen 2 at 10Gbps data rate, the total loss budget is in dB and includes all interconnect channel losses. The loss budget includes any losses in the path from the silicon to the connector, such as the silicon package, PCB traces, vias, flex, common mode filters and connectors.
For USB Type-C Gen 2 systems to maintain good signal quality without limiting PCB size and device placement, redrivers are the most cost-effective solution.
Considering a system like a smartphone or tablet, it can be thought of as high frequency digital signals coming from the APP processor package and pins, PCB traces, through holes, connectors, flex cables and USB connectors, These high data rate signals may attenuate before passing through the 1m cable.
As the signal propagates through the channel, the amplitude of the signal is attenuated, and depending on the length of the channel, this attenuation may be sufficient to cause signal integrity problems at high data rates.
A redriver acts as a signal conditioning device that restores a signal that has been lost on a given channel, it enhances the output of the restored signal, allowing the signal to travel longer distances and opening eyes to reduce bit error rates.
Redrivers with programmable differential output voltages ensure that drive strength is consistent with line impedance, trace length, and equalizes signals and resolves signal integrity issues. Remember that increasing the differential output voltage of the driver will help improve the received signal, but will also increase noise and jitter.
Maintaining acceptable signal integrity requires attention to skin effect, matched terminations, reflections, vias, crosstalk, coupling and their effects on signal attenuation.
Any interconnect should be considered a transmission line when the length of the trace is about 1/10 the wavelength of the signal.
Factors that affect signal integrity, such as channel loss and signal reflections caused by impedance mismatches, occur during any transmission of data from the processor through the PCB, through-hole, flex cable, or from the PCB, through-hole, flex cable to the processor middle.
Maintaining impedance matching throughout the signal path is critical for the interface to prevent reflections and provide maximum power transfer. Any impedance mismatch will cause reflections on the line, increasing jitter and possibly compromising signal quality.
Without a redriver, it would be difficult or nearly impossible to pass system electrical and protocol compliance tests at data rates > 10Gbps. When short-lane and long-lane testing is performed without redrivers, the total transmission channel distance for a given signal with higher data rates may be limited and the chances of interoperability between different devices reduced.