“Some applications of ADC services include ultra-high-speed multi-carrier cellular infrastructure base stations, telecommunications, digital pre-correction observations and backhaul receivers, etc.-All these applications gradually require ADCs to sample in the gigabit sampling interval per second. Part 1 and Part 2 of this analog basics series discussed successive approximation register (SAR) and delta integral (ΔƩ) ADCs, and how to use these ADCs in corresponding applications. However, neither of these two technologies can meet the challenge of generating giga-samples-per-second (GSPS) results.
Some applications of ADC services include ultra-high-speed multi-carrier cellular infrastructure base stations, telecommunications, digital pre-correction observations, and backhaul receivers, etc.-All these applications gradually require ADCs to sample in the gigabit sampling interval per second. Part 1 and Part 2 of this analog basics series discussed successive approximation register (SAR) and delta integral (ΔƩ) ADCs, and how to use these ADCs in corresponding applications. However, neither of these two technologies can meet the challenge of generating giga-samples-per-second (GSPS) results.
For example, SAR ADCs use a “snapshot” algorithm, and due to the serial method, the speed is limited to no more than 10 mega samples per second (MSPS). When using the oversampling algorithm of the high-resolution ΔƩ ADC, additional time will be required to collect multiple samples and average them to generate a 24-bit output data rate of up to 5 megahertz (MHz). The GSPS rate far exceeds the sampling frequency range of SAR ADC and ΔƩ ADC.
The pipelined ADC is the solution to the challenge of this ultra-high-speed ADC. It can process multiple samples while still sending data to its output at the speed of GSPS.
This article briefly compares ΔƩ, SAR, and pipelined ADCs, and then discusses issues related to achieving high-speed converter outputs, and why pipelined ADCs are ideal replacements for such high-speed applications. Then introduce two pipeline ADCs from Texas Instruments, one of which emphasizes accuracy, the other emphasizes high speed, and finally how to start using these ADCs.
What is a pipeline ADC?
The pipeline ADC is composed of multiple consecutive stages. The first stage adopts a differential structure, first evaluates the value of the most significant bit (MSB), then adjusts the signal, and passes it to the next stage for MSB-1 conversion. Each stage performs operations in parallel with other stages (Figure 1).
In Figure 1, the functions of each level are similar, and only one or two digits are parsed. Each stage has sample-and-hold, low-resolution flash ADC and signal conditioning functions. The first level receives samples and immediately produces MSB decisions. The MSB digital value enters the first latch (Latch 1). If the MSB decision is 1, then this stage will subtract the MSB value of the charge from the sample. Then, the pipeline converter applies a gain factor of 2 to the remaining charge. When one stage completes its operation, the simulated difference is passed to the subsequent stage. If the design uses 2 times the gain multiple, its advantage is that the first to nth stages are basically the same circuit.
The number of stages usually matches the number of ADC bits. The final conversion output combines the digital results of each stage in the output latch. This conversion process will cause a data delay of several clock cycles.
ΔΣ, SAR and pipeline ADC sampling comparison
The ΔΣ converter uses an oversampling algorithm to implement a finite impulse response (FIR) or infinite impulse response (IIR) digital filter. In the process of collecting multiple samples, these filters will produce signal output delay or delay, but the advantage is that they can achieve extremely high resolution. Therefore, the acquisition time is longer than SAR or pipeline converter, the latter two samples the signal only once during each conversion (Figure 2).
The SAR ADC uses a defined time acquisition point to render a snapshot of the input signal. When using charge redistribution technology, SAR quickly completes zero-delay conversion. The pipeline converter uses under-sampling technology to achieve high-speed conversion through the use of charge redistribution technology and the way the delayed result appears at the output. This conversion algorithm will cause data delay.
The delay and conversion speed between SAR, pipeline, and ΔƩ converter are all different (Figure 3).
In Figure 3, the ΔƩ converter averages multiple samples of each conversion result. The average filter of ΔƩ is usually FIR or IIR digital filter. This multiple sampling averaging operation will increase the total conversion time. However, high resolution can be achieved, resulting in a throughput time/accuracy correlation.
The conversion time of the SAR converter includes the input signal acquisition time and the conversion time. The acquisition time allows the input signal to stabilize before the signal acquisition actually occurs. Throughput time is the combination of internal charge redistribution and continuous serial data output signal (starting from the MSB value).
Using a pipelined ADC, the user can use the rising (or falling) edge of the external input clock to initiate sample acquisition. The charge collected for this sample enters the second stage, while the converter captures the charge equivalent to another input signal, and the second stage determines the MSB value. On the subsequent external clock, the second collected signal enters the second stage, while the first signal enters the third stage. In this clock period, the MSB-1 of the first acquisition signal and the MSB of the second acquisition signal will be determined. This process will continue with each acquired signal. When the input signal has a complete digital output representation, the output stage of the converter presents a parallel representation of the input signal.
As a result of this architecture, pipelined ADCs are popular because their sampling rates range from a few trillion times per second to more than 1 GSPS. The resolution ranges from 8 bits with a faster sampling rate to 16 bits with a slower sampling rate. These resolutions and sampling rates cover a wide range of applications, including charge-coupled device (CCD) imaging, ultrasound medical imaging, digital receivers, base stations, digital pre-correction, and digital video. Some of these applications place great emphasis on accuracy and speed.
Precision pipeline ADC
A typical example of a precision pipelined ADC is Texas Instruments’ ADC16DX370, which is a 16-bit, 370 MSPS dual-channel pipelined ADC followed by a back-end 7.4 gigabits per second (Gb/s) JESD204B interface. When the input signal is 150 MHz, the signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR) and noise spectral density (NSD) of ADC16DX370 are 69.6 decibels (dBFS), 88 dBFS and -152.3 dBFS/Hz, respectively.
Each ADC has an input buffer and an imbalance correction circuit, as well as the necessary reference voltage with an internal driver. The integrated input buffer eliminates the charge and charge kickback noise of the internal switching sampling capacitor. The buffer eases the driver amplifier, anti-aliasing filter, and impedance matching requirements (Figure 4).
ADC16DX370 uses a low-noise receiver and clock divider to obtain the sampling clock from the CLKIN input. The input clock divider distributes the high-frequency clock signal throughout the system and divides it locally on the ADC device to avoid coupling common intermediate frequency (IF) signals to other parts of the system. The core delay of the ADC is 12.5 clock cycles (Figure 5).
Sampling occurs on the rising edge of the (CLKIN+) − (CLKINC) differential signal. As the minimum core value, the digital output code is available after a data delay of 12.5 clock cycles. The CLKIN input divider factor is 1, 2, 4, or 8.
ADC16DX370 has differential clock input pins. The internal termination of each pin to DC is a 50 ohm (Ω) resistor, which can achieve a total internal differential termination of 100 Ω. The clock input pin requires external AC coupling.
The dual-pipeline ADC printed circuit board design is critical to achieving full performance. In order to fully route all signals to the inside and outside of the device, at least six layers are required. The signal routing layer requires an adjacent solid ground plane to control the signal return path to minimize the loop area, and the microstrip line and strip line must be carefully routed to control impedance. If a power plane and an adjacent solid ground plane are used, the power return path can be controlled. In addition, minimizing the distance between the power plane and the ground plane can increase distributed decoupling and improve performance.
Target applications for ADC16DX370 include high-IF sampling receivers, multi-carrier base station receivers, and multi-mode and multi-band receivers that complement the higher resolution and 370 MSPS conversion speed. This 16-bit pipelined ADC also provides the necessary SNR (69.6 dBFS) performance, for example, to distinguish small signal from background noise in the radio frequency heterodyne receiver subsystem.
To help designers evaluate ADC16DX370, ADC16DX370EVM evaluation board and related High-Speed Data Converter (HSDC) Pro software support the ADC. A mini-USB cable is attached to the EVM to connect to the PC. TI also provides the TSW16DX370EVM reference design board, which can be used to evaluate receiver IF subsystem solutions with a usable bandwidth of more than 100 MHz.
High-speed pipeline ADC
In applications that require high speed and wide dynamic range, designers can switch to Texas Instruments’ dual-channel 12-bit, 1 GSPS ADC ADS54J20. The ADC is designed to provide a high SNR of 67.8 dBFS and a noise floor of -157 dBFS/Hz. This ADC is ideal for applications that require the highest dynamic range over a wide instantaneous bandwidth (Figure 6).
In Figure 6, the interleaving and dithering algorithm of ADS54J20 is used to achieve a clean spectrum with high SFDR. The device also has a variety of programmable decimation filtering options, suitable for systems that need to achieve higher SNR and SFDR over a wide frequency range.
The band-pass decimation filter has a digital mixer and three FIR filters in series, which can produce a delay of approximately 134 output clock cycles, plus a logic gate and output buffer propagation delay equal to 4 nanoseconds (ns) (Figure 7).
The digital block, interleaving engine and decimation filter (see also Figure 6), combined with the 1 GHz high-speed sampling clock frequency, together constitute the delay of the converter.
Some of the target applications of the ADS54J20 include radar and antenna arrays, broadband wireless and cable modem termination systems (CMTS) and DOCSIS 3.1 receivers.
The evaluation board (ADS54J20EVM in this example) also supports ADS54J20 (Figure 8).
ADS54J20EVM can also be used with HSDC Pro software, and comes with a mini USB cable for connecting to a PC and a power cable.
Although SAR and ΔƩ ADCs have their own strengths, pipeline ADCs are the solution to the challenges of ultra-high-speed ADCs. While processing multiple samples, a pipelined ADC can still send data to its output at a rate of hundreds of thousands to giga-samples per second. Nevertheless, not all pipeline ADCs only emphasize speed. As mentioned above, higher accuracy can also be achieved.
Needless to say, pipeline ADCs are an excellent choice for high-speed cellular base stations, ultra-high-speed multi-carrier cellular infrastructure base stations, telecommunications, digital pre-correction observations, backhaul receivers, and many other applications that require high-speed conversion.