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Design of Bioelectric Signal Data Acquisition Based on Interface Chip and FPGA Device

Bioelectrical signals are unstable weak electrical signals sent by living organisms, mainly including ECG, EMG, and EEG signals, which are characterized by weak signals, strong interference and high levels. Therefore, in the multi-parameter measurement of organisms, high is particularly important, which puts forward higher requirements for signal acquisition rate, real-time and accuracy.

1 Introduction

Bioelectrical signals are unstable weak electrical signals sent by living organisms, mainly including ECG, EMG, and EEG signals, which are characterized by weak signals, strong interference and high levels. Therefore, in the multi-parameter measurement of organisms, high is particularly important, which puts forward higher requirements for signal acquisition rate, real-time and accuracy.

According to the characteristics of bioelectrical signals, a bioelectrical signal data acquisition system based on Ez-USB FX2 interface is introduced. It combines the advantages of traditional medical instruments with the powerful data storage capacity of computers and good human-machine interface, which is in line with the digitalization of medical instruments. , the development trend of modularization and miniaturization, and has a good application prospect.

2 Introduction to EZ-USB FX2 Interface

High-speed devices usually have a USB controller that supports high-speed transmission to achieve high-speed transmission. The built-in enhanced microprocessor 8051 and the USB2.0 controller EZ-USB FX2 (CY7C68013) that can dynamically load firmware are selected. It has powerful functions, less development difficulty and higher cost performance.

2.1 Basic Features

EZ-USB FX2 has powerful functions. It is not only responsible for USB transaction processing, but also has the control function of microprocessor. It can be used as a USB peripheral master device. The device integrates USB2.0 transceiver, serial interface engine, enhanced 8051, I2C bus and general programmable interface. It is small in size and high in cost performance. It is widely used in various USB peripherals such as memory, printers and scanners.

2.2 Endpoint Cache

The USB specification defines an endpoint as the starting point for sending data or the destination address for receiving data. The EZ-USB FX2 contains three 64 B endpoint buffers and a 4 KB configurable endpoint buffer. Three of the 64 B buffers are used for EP0, EPlIN and EP1OUT, while the 4 KB configurable buffers are used for EP2, EP4, EP6 and EP8. Endpoint 0 is a control endpoint by default, supporting OUT and IN bidirectional transmission; endpoint 1 supports batch, interrupt and synchronous transmission; and endpoints 2, 4, 6 and 8 are high-bandwidth data transmission endpoints, which can be configured in different ways to suit different bandwidth requirements.

2.3 GPIF interface

The EZ-USB FX2 family of devices offers 3 available interface modes: port mode, slave FIFO mode and GPIF master control mode. In port mode, all I/O pins can be used as general-purpose I/O interfaces of 8051; in slave FIFO mode, external logic or external processor is directly connected to the endpoint FIFO of EZ-USB FX2, and the external device acts as a controller, such as Ordinary FIFO reads and writes the endpoint data buffer in EZ-USB FX2; while GPIF mode is an internal host control mode, which uses the internal integrated high-efficiency control logic to control the Ez-USB FX2 endpoint FIFO instead of an external microcontroller. Inside the EZ-USB FX2, the GPIF core is a programmable state machine.

The EZ-USB FX2 uses 4 user-defined waveform descriptors to control the state machine. Thus, the read and write operations of FIFO and single-byte data are realized. Each GPIF waveform descriptor consists of 7 segments: S0 to S6. After performing the actions of S0 to S6, it enters the idle state (S7), that is, the idle state, in order to prepare to start the next GPIF action. Each state can be defined as a no-decision-no-transition state (NDP) or a judgment-transition state (DP). When a state is defined as NDP, the execution of this state action is just a simple delay, which is used to determine the duration of generating the specified level; when it is defined as DP, it will be based on the input signal state on RDY0~RDY5 and the internal The programmable flag of the FIFO and the internal self-defined Ready flag perform logical “AND”, “OR” and “XOR” operations on these signals, and select a state to be executed in S0-S6 according to the obtained logical result. When executing each state, CTL0 to CTL5 can be specified to output the user-specified state. Through the combination of RDYx and CTLx and some internal flag bits, the control of various complex sequential circuits can be completed. Due to the flexible configuration of the GPIF interface, FX2 can easily read and write data with other logic microprocessors (such as single-chip microcomputer, DSP, CPLD, and FPGA, etc.), which greatly expands the scope of use of the GPIF mode. In GPIF mode, 8051 can not participate in data transmission, to break through the high-speed, full-speed transmission mode and further approach the transmission bandwidth of EZ-USB FX2 480 Mb/s. At the same time, according to the frequency characteristics of bioelectric signals, the sampling frequency of each channel is set to 100 kHz, which can fully meet the system requirements in GPIF interface mode.

3 System structure

The system structure frame is shown in Figure 1. After the ECG, EEG, EMG and other signal conditioning circuits collected by the human body through the lead, the A/D conversion is controlled by the internal logic of the FPGA to sample it. Temporarily buffer the sampled and A/D converted data into the internal FIFO of EZ-USB FX2 for PC reading. The whole system involves A/D conversion and its channel selection, signal amplification, FPGA control and EZ-USBFX2 interface design. Here we mainly introduce the EZ-USB FX2 interface design, as well as the development of the corresponding firmware program and GPIF waveform design.

Design of Bioelectric Signal Data Acquisition Based on Interface Chip and FPGA Device 

4 Device Resource Allocation

4.1 Hardware connection between EZ-USB FX2 and FPGA

EZ-USB FX2 uses GPIF interface to connect with FPGA, and its hardware connection circuit is shown in Figure 2. The pin assignments between EZ-USB FX2 and FPGA are as follows: FD0~FD15 are GPIF bidirectional data lines, responsible for reading and writing data: CTL0 and CTL1 are read (REN#) and write (WEN#) enable signals respectively; RDY0 is FPGA The sent data is ready signal; PA2 is connected to the H4 pin of the FPGA to light up the LED when the data acquisition starts.

4.2 Endpoint Assignment

The data channel in the system is divided into a data upload channel and a configuration and control command channel. According to the design needs, two endpoints are selected as the sending and receiving endpoints respectively. The configuration is as follows: EP2 is used to transmit acquisition control commands from USB to FPGA, with a 4×512-byte buffer, and the transmission type is batch OUT transmission; EP6 is used to transmit data acquisition results from FPGA to USB, with a 4×512-byte buffer, transmission The type is batch IN transmission. EZ-USB FX2 is equivalent to a transfer station. On the one hand, it transmits the acquisition data sent by the FPGA to the host, and on the other hand, transmits the data acquisition parameters sent by the host to the FPGA, which is convenient for controlling A/D conversion.

5 Firmware programming

The firmware is run by the device, and its main function is to control EZ-USB FX2 to process driver requests (such as requesting device descriptors, requesting or setting USB2.0 standard requests such as device status and device interfaces), sending acquisition parameters to FPGA, and sending acquisition parameters to FPGA. -USB FX2 caches data and uploads it to PC in real time, etc.

In this system, even if external logic and built-in general programmable interface are used, high-speed bandwidth data can be processed through 4 endpoint FIFOs without CPU intervention. The firmware also needs device initialization, GPIF waveform initialization, and control and monitoring of GPIF actions.

5.1 Device initialization

The initialization function of the same piece is TD_Init(), which is mainly responsible for the initialization of EZ-USB FX2, and it is called when the same piece starts to run. Its initialization work is mainly divided into the following steps:

(1) Set the IFCLK output frequency of EZ-USB FX2, and set the clock frequency to the internal clock 48 MHz;

(2) Set EP2 of EZ-USB FX2 as BULK, OUT transmission mode, EP6 as BULK, IN transmission mode, both are 4 times buffer;

(3) Reset EP2 FIFO and set it to Auto OUT mode, reset EP6FIFO and set it to Auto IN mode;

(4) Call the GpifInit() function to initialize the registers required by GPIF; use the EF flag for EP2OUT and GPIF, and use the FF flag for EP6IN and GPIF;

(5) Initialize PA2 as an output pin and set it to a low level, and light up the LED when it is high.

5.2 GPIF waveform design

The EZ-USB FX2 firmware program can specify a waveform to work for any one of the 4 endpoints, and the GPIF will generate an enable signal and a handshake signal on the interface to send data into or out of the endpoint FIFO. In this system, when writing commands to the FPGA, it is realized by FIFO Write; when reading the collected data, it is realized by FI-FO Read. The waveform design is as follows:

(1) Figure 3 shows the FIFO Write timing waveform, which is used to send acquisition control parameters to the FPGA. S0 is inactive state. When WEN# is set low, it jumps into S1 state, S2 is set to Next FIFO Data, and the data is written into the registers of the FPGA in turn.

(2) Figure 4 is the FIFO Read timing waveform, which describes the read transmission of the collected data, S0 is the inactive state, S1 is the leading state of the read operation and REN# is set low. After receiving DataRDY=1 sent by FPGA, jump to S2. Set S2 as FlowState, the logic control data is read from the FPGA and the state of REN# is manipulated, that is, when Tcxpire=1, REN# is set high and jumps into the IDIE state. In the FlowState state, WEN# is set high and the write enable is turned off.

5.3 Data collection process

At the beginning of the program, the main function calls the TD_Init() and Gpiflnit() functions, initializes the registers, and transfers the generated GPIF waveform program into the RAM of the device through the two automatic pointer registers AUTOPTR1 and AU-TOPTR2, and then the state machine starts to run, generating The designed control waveform. After the acquisition parameters are downloaded, the FPGA parses the parameters, delays, and EZ-USB FX2 sends a read enable signal to the FPGA to start data acquisition. The data acquisition program flow is shown in Figure 5. If the FP-GA returns DataRDY=1, execute the read data transfer procedure in the TD_Poll() function. After completing the process, the program starts to upload data automatically according to the host’s request.

6 Conclusion

The data acquisition system based on FPGA control circuit and EZ-USB FX2 high-speed transmission can simultaneously collect 16-bit bioelectrical signals; EZ-USB FX2 adopts GPIF interface mode, 8051 can not participate in data transmission, in order to break through the transmission mode under high-speed and full-speed, Solve the problem of transmission bottleneck between peripheral devices and EZ-USB FX2 interface: At the same time, A/D conversion is separated from EZ-USB FX2, and is completely controlled by FPGA, which avoids data loss when uploading directly. The system design has the advantages of simple structure, no data loss and high transmission rate, so it has good practical value and application prospect in bioelectric signal data acquisition.

The Links:   IP4283CZ10-TBA 6DI50M-050

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