“A motion controller based on CAN bus is designed by using low-power Cortex-M3 microcontroller STM32F103VBT6 and FPGA chip. The system architecture, main hardware design and software structure are introduced. The high-speed processing capability of FPGA is used to realize the control algorithm, and STM32 and CAN bus technology are used for communication with the outside world. The system is stable and reliable. In addition, the designed FPGA program or C program is encapsulated, and the system is highly portable.
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A motion controller based on CAN bus is designed by using low-power Cortex-M3 microcontroller STM32F103VBT6 and FPGA chip. The system architecture, main hardware design and software structure are introduced. The high-speed processing capability of FPGA is used to realize the control algorithm, and STM32 and CAN bus technology are used for communication with the outside world. The system is stable and reliable. In addition, the designed FPGA program or C program is encapsulated, and the system is highly portable.
Today, motion control is developing in the direction of high speed, high precision, and openness, which puts forward higher requirements on the execution components. In the past, motion controllers were mainly based on single-chip microcomputer or PLC plus discrete digital circuit design, which was limited by the performance of the device itself, resulting in slow circuit execution, bulky, low integration, and difficult upgrades. The only control system composed of modern means such as microprocessor, DSP and FPGA is the development direction of a new generation of motion control. In this paper, the embedded motion controller based on FPGA is studied, and CAN bus is applied, which makes the hardware interface simple, real-time and flexible, and has strong practical value.
1 Overall scheme design
Strategy This system is based on the Cortex-M3 processor STM32F103VBT6 chip core produced by STMicroelectronics for communication, data storage, keyboard scanning and LCD Display. It integrates CAN, SPI, USB, and USART controllers to meet the design of the system. Requirements, the realization process of the simplified system, and the rich function library greatly shorten the user’s development cycle. As the main executive body of the system, FPGA uses its high speed for algorithm realization, speed control and position control. The overall structure of the system is shown in Figure 1.
2 Functional module design of motion controller
In order to meet the operation of the whole system, motion control is mainly composed of two parts: communication and data processing. Communication and data storage are carried out by STM32. Due to the complexity and real-time nature of data operations, FPGA processing algorithms are implemented. This design is relatively large, and the modules are not introduced one by one.
2.1 Design of CAN Communication Module
2.1.1 Hardware Design
bxCAN is the built-in CAN controller of STM32, supports 2.0A and 2.0B CAN protocols, the baud rate can reach up to 1 Mbit/s, contains 3 send mailboxes, 2 receive FIFOs with 3 levels of depth, 14 variable The bit-wide filter group supports time-triggered communication mode. Its design goal is to efficiently process a large number of received messages with minimal CPU load. It also supports priority requirements for message sending (the priority feature can be configured by software). ). The CAN hardware design is shown in Figure 2.
Using CTM8251 as the transceiver chip, it can not only complete the transceiver function, but also has the isolation function of DC2500V, which isolates the system from the outside world, simplifies the hardware design of the CAN peripheral, and improves the cost performance of the system. The resistance of 120Ω in the figure is optional If there is already a pair of matching resistors in the network, this resistor can not be used. Among them, B82790 is a common mode choke coil, and its function is to suppress common mode interference and balance the transmission of differential signals; in this design, the more commonly used The DIP switch circuit sets the ID address and baud rate of the CAN network; the LED is used as a communication status indication.
2.1.2 Software Design
For the setting of STM32 peripherals, we only need to configure the corresponding parameters appropriately to meet the design requirements. The main tasks of the software part only need to perform CAN initialization and data transmission. In the initialization module of this design, only the CAN working mode needs to be configured, and no special configuration of the filter is required. Some initialization procedures are as follows:
The most important thing in the configuration of the working mode is the configuration of the baud rate. In this design, AHB1 is used as the CAN clock of 36 MHz, so to get a baud rate of 1 Mbit/s, the above settings are made, that is, SJW=tq, BS1= 3tq, BS2=5tq, CAN_Prescaler=4, so the baud rate is calculated as follows:
2.2 Design of FPGA Circuit
The FPGA circuit mainly realizes the related algorithms of motion control, including acceleration and deceleration algorithm, detection device algorithm, interpolation algorithm and other algorithms, which is the key part of the whole design. The hardware design mainly includes the power supply circuit, clock circuit and configuration circuit of the FPGA. It is a relatively conventional circuit and will not be introduced here. The implementation of related algorithms is mainly introduced in this paper.
2.2.1 Acceleration and deceleration module
In order to avoid some unwanted phenomena such as shock, over-travel, loss of step and oscillation during motor operation and speed change when the motor is started. In order to enable the actuator to be positioned smoothly and accurately, it is required that the motor has a process of acceleration and deceleration during the process of starting the motor until the speed of the motor reaches the given feed speed, so that it can transition smoothly. Avoid sudden changes in speed to damage the motor.
S-curve acceleration and deceleration is an ideal control acceleration and deceleration method, but how to ensure the smooth and accurate construction of the curve has become the focus of many algorithm engineers’ research. As shown in Figure 3, in the process of acceleration, there are 3 different acceleration regions. In the initial stage, the acceleration is linearly increased from 0 to a fixed acceleration value A at a certain acceleration rate K. That is to say, at this time, the driving speed increases in a parabolic manner in the a region; then in the b region, the driving speed The speed increases with a constant acceleration; finally, in the c region, the acceleration decreases linearly to 0 according to the acceleration rate K. In this way, the acceleration process of the S curve can be regarded as composed of three regions a, b, and c. . In the process of deceleration, like the acceleration process, the deceleration in the d, e, and f regions is also parabolic.
The corresponding functions of velocity, acceleration, and time constructed based on this design are as follows:
The realization of S acceleration and deceleration in FPGA is shown in Figure 4. The S acceleration and deceleration curve can be obtained when the given acceleration A, acceleration rate K, initial speed V0, feed speed V and the total number of pwm pulses are known.
Figure 5 is the simulation waveform of this design in Quartus II. In order to speed up the simulation, some parameters have been modified before the simulation.
The structure of the acceleration and deceleration module of this system satisfies the structure of the speed and acceleration curve to meet the conditions of stable speed change and continuous acceleration, the starting and ending speeds are consistent with the required speed, the acceleration is 0, and the acceleration rate K can be adjusted at any time according to actual needs. Sex is good.
2.2.2 Photoelectric encoder module
The closed-loop control used in this system, the accuracy of the feedback signal directly affects the positioning and speed measurement. Here, the incremental encoder is used for positioning control. The incremental encoder mainly uses two square wave signals A and B with a difference of 90 degrees. and the zero pulse signal Z for angular displacement and direction judgment (as shown in Figure 6), so as to achieve the purpose of detecting the position. In addition, if we quadruple the frequency of the A or B signal, the period of the counting pulse will be reduced to T /4, so that the angular displacement measurement accuracy is increased by 4 times. The encoder signal after quadrupling frequency can be converted into relative position only after being counted by the counter. A traditional waveform conversion circuit is composed of two NAND gates, a non-gate logic and D flip-flops, through which A-phase and B-phase pulses are converted into forward count signal dz, reverse count signal df and direction (dir) signal , the final count is completed by adding and subtracting digital signals in the forward and reverse directions, and the final simulation data is shown in Figure 7.
3 Conclusion
The research of this subject is based on the summary of the control system design of a certain brand of engraving machine, aiming to establish a general motion controller. The control requirements are met. The communication is very stable, and the related algorithms still need to be optimized.
The Links: G150XTN060 NL6448BC18-01B
