“Efficiency is often the most important factor when designing power supplies for many types of consumer and industrial applications, including cell phones, tablets and laptops, rechargeable power tools and LED lighting, among countless other products. Some applications require high efficiency to meet statutory requirements or simply reduce heat dissipation for smaller, lighter end product designs. Selecting a synchronous MOSFET to meet all these requirements can be a difficult task.
Efficiency is often the most important factor when designing power supplies for many types of consumer and industrial applications, including cell phones, tablets and laptops, rechargeable power tools and LED lighting, among countless other products. Some applications require high efficiency to meet statutory requirements or simply reduce heat dissipation for smaller, lighter end product designs. Selecting a synchronous MOSFET to meet all these requirements can be a difficult task.
Of course, engineers will first look at the obvious data sheet parameters to select a device with the appropriate voltage and current ratings. Since efficiency is important, most devices are selected first by RDS(on). The dynamic parameters are then chosen depending on the switching frequency; for example, the gate charges Qg and Qgd are a good indicator of the expected losses at the gate. The Qg figure of merit (FOM = RDS(on) x QG) can also be a good indicator of the efficiency of the MOSFET in switching applications, while the capacitance of the MOSFET, Ciss, Coss, Crss, can reflect whether drain-source spikes and gate disturbances will become a problem. Low capacitance also helps improve efficiency. Finally, the device must fit into your design, so you need to look at its size and package.
However, there is another parameter Qrr that is often overlooked and it is usually located at the bottom of the data sheet. In applications where current flows through the body diode of a MOSFET, such as in synchronous rectifiers and freewheeling applications, the reverse recovery charge Qrr presents some significant challenges that the design engineer needs to deal with carefully.
Qrr or reverse recovery charge is the charge that accumulates in the PN junction of the MOSFET body diode when the diode is forward biased. In most applications, current flows through the body diode twice per switching cycle, causing charge accumulation. Subsequent charge discharge, either inside the MOSFET or briefly flowing through the high-side MOSFET as an additional current (Irr), causes additional losses in the system.
The reverse recovery current (Irr) also interacts with the parasitic inductance of the PCB, causing the drain-source voltage (VDS) to spike. These spikes can be reduced by reducing the inductance of the PCB or choosing a MOSFET with lower Qrr. Failure to address the spikes at the design stage often results in engineers having to use higher voltage levels, thus requiring more expensive MOSFETs later in the project.
But that still leaves a question. If left untreated, spikes on the drain pin can be capacitively coupled to the gate pin, causing what is known as “gate perturbation”. If the gate disturbance exceeds the threshold voltage of the MOSFET, cross-conduction occurs, and the MOSFET may turn on when it should be turned off. If both the high-side MOSFET and the low-side MOSFET are turned on at the same time, shoot-through current will develop between the power rails, causing large power losses and potentially damaging the MOSFETs.
Let’s examine this issue in more detail. During the dead time required for most applications, current flows through the body diode twice per switching cycle. Let’s first consider what happens before the synchronous FET turns on. Since the current will flow through the body diode during the dead time, some of the load current will be trapped as accumulated charge (Qrr).
When the synchronous FET is turned on, the accumulated charge is released inside the MOSFET. Therefore, part of the load current is lost due to the Qrr effect, resulting in I2R losses within the synchronous FET.
In the second case, when the high-side MOSFET is turned on, the body diode of the MOSFET is reverse biased again. The additional current Irr briefly flows through the high-side MOSFET until the accumulated charge Qrr is completely depleted. Charge depletion is not instantaneous, Irr typically flows for tens of nanoseconds until Qrr is depleted. The reverse recovery time Trr is quoted in the data sheet. In this case, Irr causes additional I2R losses in the high-side MOSFET.
The reverse recovery current spike Irr also interacts with the parasitic inductance of the PCB, creating a voltage spike where:
V = L x (di/dt).
The withstand voltage of the MOSFET should be chosen appropriately to ensure that the breakdown voltage rating (BVDS) is higher than the maximum peak value; 80% derating is usually used. When the measured peak value is 80V, the withstand voltage of Vds generally requires a MOSFET with a BVDS of at least 100V.
Designers should also look at gate perturbation in their applications when Vds spikes occur. Since there is capacitance between all three terminals of the MOSFET, any spikes on the drain pin will also be capacitively coupled to the gate pin of the MOSFET. In extreme cases, if the gate disturbance exceeds the threshold voltage of the MOSFET, the MOSFET goes into an on state.
The pre-driver circuit usually needs to set the dead time to ensure that the high-side MOSFET and the low-side MOSFET cannot be turned on at the same time. However, when gate disturbance occurs, the low-side and high-side MOSFETs are turned on simultaneously, causing shoot-through current to flow between the power rails, causing excessive I2R losses and, in extreme cases, MOSFET damage.
All MOSFETs are not created equal
For 100V MOSFETs, when comparing the datasheet parameters of different MOSFET suppliers in the 4~8mΩ on-resistance range, it can be seen that there is a large difference in the Qrr of different suppliers. For MOSFETs with similar on-resistance, Nexperia’s NextPower 100V technology provides Qrr typically 30% to 100% lower than other MOSFET suppliers.
In typical applications, because it is difficult to isolate and measure individual Qrr effects, we rely on simulations to model their effects.
A Spice simulation of the 7mΩ MOSFET PSMN6R9-100YSF shows that when Qrr is doubled, the resulting spike voltage can increase by about 8%, as shown in Figure 2.
Figure 1: Spice simulation of a 7mΩ MOSFET shows that when Qrr is doubled, the resulting spike voltage increases by about 8%
Choosing a low Qrr MOSFET can also significantly improve efficiency, especially at low load currents.
In the application of low-power chargers and adapters, the switching frequency is high and the load current is generally less than 5A. Less attention is paid to the I2R loss, and the design engineer should pay close attention to the dynamic loss. Choosing a low-Qrr MOSFET can reduce spikes, improve efficiency, and reduce EMI emissions, as shown in Figure 3.
Figure 2: Low Qrr MOSFETs can reduce spikes, improve efficiency, and reduce EMI emissions