Freescale’s MCF51QE128 series are pin-compatible 8-bit and 32-bit Flexis series MCU devices, using 32-bit Version 1 ColdFire CPU, operating voltage greater than 2.4V is the frequency up to 50.33MHz, greater than 2.1V is the frequency up to 40MHz, greater than 1.8V It is a frequency up to 20MHz, providing 0.94 Dhrystone 2.1MIPS/MHz performance, mainly used in industrial and industrial automation, medical equipment such as blood pressure monitors, ECG monitors, patient care beds, blood glucose meters, etc. This article introduces the main features of the MCF51QE128 series , block diagram, and blood pressure monitor reference design key features, block diagram, blood pressure monitor (BPM) software flowchart and circuit diagram and bill of materials.
The QE family, comprised of a pin-compatible 8-bit and 32-bit device duo, is the first family in the Flexis series. The FlexisTM series of controllers is the connection point on the Freescale Controller Continuum, where 8- and 32-bit compatibility becomes reality.
The MCF51QE128 device extends the low end of the 32-bit ColdFire controller family with up to 128 KB flash memory and a 24-channel, 12-bit analog-to-digital converter (ADC). The 32-bit MCF51QE128 is pin-, peripheral- and tool-compatible with the 8-bit S08QE128 device. They share a common set of peripherals and development tools delivering the ultimate in migration flexibility.
Main features of MCF51QE128 series:
• 32-Bit Version 1 ColdFire® Central Processor Unit (CPU)
– Up to 50.33-MHz ColdFire V1 CPU above 2.4V, 40-MHz CPU above 2.1V, and 20-MHz CPU above 1.8V, across temperature range
– Provides 0.94 Dhrystone 2.1 MIPS per MHz performance when running from internal RAM (0.76 DMIPS/MHz from flash)
– Implements Instruction Set Revision C (ISA_C)
– Support for up to 30 peripheral interrupt requests and seven software interrupts
• On-Chip Memory
– Flash read/program/erase over full operating voltage and temperature
– Random-access memory (RAM)
– Security circuitry to prevent unauthorized access to RAM and flash contents
• Power-Saving Modes
– Two low power stop modes; reduced power wait mode
– Peripheral clock enable register can disable clocks to unused modules, reducing currents; allows clocks to remain enabled to specific peripherals in stop3 mode
– Very low power external oscillator can be used in stop3 mode to provide accurate clock to active peripherals
– Very low power real time counter for use in run, wait, and stop modes with internal and external clock sources
– 6 μs typical wake up time from stop modes
• Clock Source Options
– Oscillator (XOSC) — Loop-control Pierce oscillator; Crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz
– Internal Clock Source (ICS) — FLL controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation; supports CPU freq. from 2 to 50.33 MHz
• System Protection
– Watchdog computer operating properly (COP) reset with option to run from dedicated 1-kHz internal clock source or bus clock
– Low-voltage detection with reset or interrupt; selectable trip points
– Illegal opcode and illegal address detection with programmable reset or exception response
– Flash block protection
• Development Support
– Single-wire background debug interface
– 4 PC plus 2 address (optional data) breakpoint registers with programmable 1- or 2-level trigger response 64-entry processor status and debug data trace buffer with programmable start/stop conditions
• ADC — 24-channel, 12-bit resolution; 2.5 μs conversion time; automatic compare function; 1.7 mV/℃ temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6V to 1.8V
• ACMPx — Two analog comparators with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal bandgap reference voltage; outputs can be optionally routed to TPM module; operation in stop3
• SCIx — Two SCIs with full duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wake up on active edge
• SPIx—Two serial peripheral interfaces with Full-duplex or single-wire bidirectional; Double-buffered transmit and receive; MSB-first or LSB-first shifting
• IICx — Two IICs with; Up to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; Interrupt driven byte-by-byte data transfer; supports broadcast mode and 10 bit addressing
• TPMx — One 6-channel and two 3-channel; Selectable input capture, output compare, or buffered edge- or center-aligned PWMs on each channel
• RTC — 8-bit modulus counter with binary or decimal based prescaler; External clock source for precise time base, time-of-day, calendar or task scheduling functions; Free running on-chip low power oscillator (1 kHz) for cyclic wake -up without external components
• Input/Output
– 70 GPIOs and 1 input-only and 1 output-only pin
– 16 KBI interrupts with selectable polarity
– Hysteresis and configurable pull-up device on all input pins; Configurable slew rate and drive strength on all output pins.
– SET/CLR registers on 16 pins (PTC and PTE)
– 16 bits of Rapid GPIO connected to the CPU’s high-speed local bus with set, clear, and toggle functionality
MCF51QE128 series target applications:
Industrial
ZigBee® for Home Area Network Metering
OFDM Power Line Modem
Fire and Security Systems
HVAC Building and Control Systems
Factory Automation
Medical
Heart Rate Monitors
Pulse Oximetry
Powered Patient Beds
Blood Glucose Monitors (Glucometers)
Electrocardiograph (ECG)
Fetal Heart Rate Monitors 
Figure 1. MCF51QE128 Series Block Diagram
Blood Pressure Monitor Reference Design Using the Flexis QE128 Series
Blood Pressure Monitor Using the Flexis QE128 Family
The Blood Pressure Monitor reference design demonstrates how the sensing, data communication and processing capabilities of Freescale products interact to create a complete medical handheld solution.
This Blood Pressure Monitor design was crafted to serve as reference for those designs that need expansion flexibility. Enabled to use both the 8-bit MC9S08QE128 and 32-bit MCF51QE128, both members of the pin-, peripheral- and tool-compatible Flexis QE128 Family , Freescale provides intelligence to medical solutions providing freedom across the performance spectrum.
The BPM reference design elements can be referenced for later development as:
• USB communication using the MC9S08JM60 as a bridge
• 2.4 GHz communication using the MC13202 ZigBee transceiver
• MRAM communications
• Use of MRAM to store user data
• MRAM driver to access MRAM memory
• User Display using an OLED display
• User interface using the MPR083 proximity sensor
• Audio feedback using two timer pulse-width modulator (TPM) modules
Blood Pressure Monitor Reference Design Key Features:
Arterial pressure measurement using up-ramp and down-ramp methods
4 language navigation menu along with voice generator functions to enunciate results (English, Spanish, French, German)
Wireless RF interface implemented with SMAC protocol to send data to other coordinators, routers or end devices.
USB connectivity to download historical data stored in MRAM (external memory).
Navigation buttons using proximity sensing
OLED for Graphical Display
Low Power techniques implementation
Figure 2. PCB Outline Drawing of Blood Pressure Monitor Reference Design (Partial)
Figure 3. Block Diagram of Blood Pressure Monitor (BPM) Reference Design
Figure 4. Blood pressure monitor (BPM) software flow chart
Figure 5. Blood Pressure Monitor (BPM) Reference Design Circuit Diagram (1)
Figure 6. Blood Pressure Monitor (BPM) Reference Design Circuit Diagram (2)
Figure 7. Blood Pressure Monitor (BPM) Reference Design Circuit Diagram (3)
Figure 8. Blood Pressure Monitor (BPM) Reference Design Circuit Diagram (4)
Figure 9. Blood Pressure Monitor (BPM) Reference Design Circuit Diagram (5)
Figure 10. Blood Pressure Monitor (BPM) Reference Design Circuit Diagram (6)
Figure 11. Blood Pressure Monitor (BPM) Reference Design Circuit Diagram (7)
Figure 12. Blood Pressure Monitor (BPM) Reference Design Circuit Diagram (8)
Figure 13. Blood Pressure Monitor (BPM) Reference Design Circuit Diagram (9)
Figure 14. Blood Pressure Monitor (BPM) Reference Design Circuit Diagram (10)
Figure 15. Blood Pressure Monitor (BPM) Reference Design Circuit Diagram (11)
Blood Pressure Monitor (BPM) Reference Design Bill of Materials (BOM):
For details, see:
http://cache.freescale.com/files/32bit/doc/data_sheet/MCF51QE128.pdf?fpsp=1
and
http://cache.freescale.com/files/microcontrollers/doc/ref_manual/DRM101.pdf
The Links: G084SN03-V0 FS75R12KT3G IGBTS
