“The ISL1561 is a fixed gain dual port class G differential amplifier design that drives ADSL2+ and VDSL2 with reduced power consumption compared to class AB amplifiers. The line driver operates from a single +12V to +14V supply and generates a higher supply voltage when a boost is detected. Quiescent current can be programmed with a 12-bit command via a 3-pin serial port interface (SPI).
The ISL1561 is a fixed gain dual port class G differential amplifier design that drives ADSL2+ and VDSL2 with reduced power consumption compared to class AB amplifiers. The line driver operates from a single +12V to +14V supply and generates a higher supply voltage when a boost is detected. Quiescent current can be programmed with a 12-bit command via a 3-pin serial port interface (SPI).
The ISL1561 is Intersil’s most efficient dual port line driver for ADSL2+ and VDSL2 applications operating from a +14V supply. A new feature supported by the ISL1561 is the programming of quiescent current through SPI. Given the target MTPR performance, the quiescent current can be adjusted accordingly to reduce power consumption (500µA steps). When transmitting 8b VDSL2, power consumption can be reduced by 25% compared to Class AB operation. The ISL1561 is very “robust” in handling transients. Passed the ITU-T K.20 standard test.
Figure 1 shows a power consumption comparison between the 8b and 17a VDSL2 profiles. For 8b 19.5dBm, ISL1561 consumes only 600mW while achieving -64dBc lost band power ratio (MBPR); for 17a 14.5dBm, ISL1561 consumes 400mW while achieving -60dBc MBPR
Figure 1 Class AB and G power consumption
Using the USB microcontroller integrated on the evaluation board, the supply current of the ISL1561 can be individually programmed for each port. The microcontroller communicates with the three pins SPI of the ISL1561 using four logic signals (SCLK, SDI, SDO and CS): (SCLK, SDATA and CS). Since SDATA of ISL1561 is used for data input and output, a 10kΩ series resistor is placed between SDI and SDO. Therefore, SDI must be connected directly to SDATA for the microcontroller to read the registers in the ISL1561.
Power Sequencing and Reset
Before power-up, the SPI pin can be left floating or pulled low. The digital interface generates an internal 5V VDD. The SPI and BOOST pins are internally biased as follows:
BOOST pin: Internally pulled up to VDD
CS pin: Internally pulled up to VDD
SDATA pin: internally pulled down to GND
SCLK pin: internally pulled down to GND
When CS is high, the serial interface counter is reset when a clock cycle is received. When CS is driven high, the SCLK pulse will reset the serial counter on the falling edge of SCLK.
The ISL1561 evaluation board can be programmed using the GUI software. Running “ISL1561_Installer_V1.0.exe” will install the required drivers for the program.
The program files will be installed in “C:Program FilesIntersilISL1561” and the file to run is “ISL1561.exe”.
NOTE: When running the program, make sure to connect the microcontroller to the computer’s USB port.
Figure 2 Window GUI
Figure 2 shows the ISL1561 starting up in disabled mode. Clicking “Read All” will cause both registers to Display “80”. Two register boxes allow the user to write and read. For example, when the user clicks the box and types “0F”, the program also returns the read register value to “0F” in the same box. If it shows a different value, the register is not programmed correctly.