Logarithmic Volume Control and Glitch Reduction Using the AD5292 Digital Potentiometer (CN0120)
Circuit functions and advantages
This circuit uses the AD5292 digiPOT+™ family of digital potentiometers, the AD8676 dual op amp, the AD8541 single op amp, the ADCMP371 comparator, and the 7408 AND gate to provide logarithmic volume control and reduce glitches.
The circuit also features low total harmonic distortion (THD) with a maximum signal attenuation of 46 dB and a shutdown function with up to 130 dB attenuation, as shown in Figure 3. Executing a software shutdown command places the AD5292 in shutdown mode, a feature that places the RDAC in a special state where terminal A is open and the wiper W is connected to terminal B.
The circuit provides logarithmic gain control, has an output voltage range of ±14 V (10 Vrms), and is capable of delivering up to ±20 mA of output current. The AD5292 can be programmed through an SPI-compatible serial interface.
In addition, the AD5292 has a built-in 20-time programmable memory that can customize volume settings at power-up.
This circuit features low noise, low total harmonic distortion, high signal attenuation, low temperature coefficient, and high voltage capability, making it ideal for many audio applications.
Figure 1. Logarithmic Volume Control for Glitch Reduction (Simplified Schematic, Decoupling and All Connections Not Shown)
circuit description
This circuit uses the AD5292 digital potentiometer, AD8676 dual op amp, AD8541 single op amp, comparator ADCMP371, and 7408 AND gate to provide low distortion logarithmic volume control and reduce glitches. The logarithmic tap is realized by adding resistor R8 between the wiper connection and ground. For a detailed description of this method, please refer to the article “Adding a Log Tap to a Digital Potentiometer” by Hank Zumbahlen (EDN, 1/20/00).
The circuit provides an input/output buffer to minimize loading effects from other external circuits. The AD8676 dual op amp ensures low noise and precision rail-to-rail output voltage. Figure 2 shows the logarithmic output voltage VIN normalized by VOUT.
Figure 2. Normalized VOUT vs. Code
The volume control guarantees a maximum attenuation of 46 dB and up to 130 dB in shutdown mode. Figure 3 shows the attenuation for a typical code, including the off mode, and the code-independent signal phase delay.
Figure 3. Gain and Phase vs. Frequency for 1 V RMS Input Signal
The circuit features low total harmonic distortion (THD), typically −93 dB for a 1 kHz, 1 VRMS input signal, as shown in Figure 4. Figure 4, Figure 5, and Figure 6 show typical total harmonic distortion plus noise performance.
Figure 4. FFT at 1 kHz, 1 kHz, 1 VRMS Input Signal, 0 dB Gain
Figure 5. Total Harmonic Distortion plus Noise (THD+N) vs. Frequency for 1 VRMS Input Signal, 0 dB Gain
Figure 6. Total Harmonic Distortion Plus Noise (THD+N) vs. 1 kHz Input Signal Amplitude at 0 dB Gain
When there is no glitch reduction circuit, the glitch caused by the large attenuation step is shown in Figure 7, and the glitch caused by the code conversion of the internal switch is shown in Figure 8.
Figure 7. Large step change in attenuation showing glitch without glitch reduction circuit
Figure 8. Small Change in Attenuation Shows Glitch Without Glitch Reduction Circuit
The glitch reduction circuit uses AD8541, ADCMP371 and 7408 AND gates. Comparators U2 and U3 act as window comparators with a 13.3 mV threshold between them, sufficient to overcome the offset voltage effects of typical comparators. The circuit is a zero-crossing detector that allows the attenuation to change only when the signal crosses 0 V, thus minimizing glitches. Resistors R4 and R5 attenuate the input signal by 90.91% and establish a common-mode voltage of 1.645 V in the window comparator. The maximum uncertainty of zero-crossing is reflected to the input at about 133 mV. The output of the window comparator is ANDed with the external SYNC command to drive the SYNC input of the AD5292. After the negative-going edge of SYNC enters the AD5292, the next clock pulse will update the internal DAC register.
Resistors R1 to R7 should be 0.1% toleranced to ensure optimal zero-crossover detection, keeping glitch energy low and preventing large step changes in attenuation. The threshold window is about 133 mV with respect to the input signal voltage VIN. A typical decay step in the AD5292 when the glitch reduction circuit is active is shown in Figure 9 (the next clock pulse updates the internal DAC register).
Figure 9. After Glitch Reduction Circuit Activation
The AD5292 has a 20-time programmable memory that allows the user to preset the attenuation to a specific value at power-up.
To achieve the desired performance, optimal layout, grounding, and decoupling techniques must be used (refer to the MT-031 tutorial and MT-101 tutorial). At least four layers of PCB should be used: one is the ground plane, one is the power plane, and the other two are the signal layers.
common changes
The AD5291 (8-bit, built-in 20-time programmable power-up memory) and AD5293 (10-bit, no power-up memory) are ±1% tolerance digital potentiometers and are also suitable for this application.
The Links: LM170E03-TLJ6 NL6448BC33-71D
