“The operation of a three-phase motor requires a three-phase inverter, which is generally composed of: 6 power transistors (MOSFETs or IGBTs), gate drivers (one or more) to control the transistors, implementation of the control algorithm (speed, torque control, etc.) control logic circuit (microcontroller or microprocessor).
The operation of a three-phase motor requires a three-phase inverter, which is generally composed of: 6 power transistors (MOSFETs or IGBTs), gate drivers (one or more) to control the transistors, implementation of the control algorithm (speed, torque control, etc.) control logic circuit (microcontroller or microprocessor).
Gate drivers are the analog bridge between digital control and power actuators, they must be reliable, robust against noise and disturbances, accurate (guarantee control algorithms and pulse width modulation are effective), and for safe operation, they must operate under unconventional conditions protection and safety functions are required during the downtime or during the failure of a part of the system.
STMicroelectronics STDRIVE601 is a single-chip integrated three half-bridge gate drivers for N-channel power MOSFETs and IGBTs. The chip uses ST’s BCD6s-high voltage technology, which integrates bipolar, CMOS and DMOS devices on the same chip with floating cells that drive high-side transistors with breakdown voltages in excess of 600V. Next-generation BCD6s technology ensures the device’s best-in-class robustness.
The device also has several auxiliary functions and features that help speed up system design and reduce peripheral components and circuits. Avoid complex and trivial protection circuits against noise and disturbances and keep the entire application simple and economical.
The STDRIVE601 is available in a small SO28 package and can replace three half-bridge drivers to simplify PCB layout. All 6 outputs can achieve 350mA sink current and 200mA source current, and the gate drive voltage range is 9-20V.
The three high-side bootstrap cells operate up to 600V and can be powered by built-in bootstrap diodes, saving PCB area and reducing component count. Low-side and under-voltage lockout (UVLO) features on each high-side driver unit prevent power switches from operating in inefficient or dangerous states.
Due to technological development and design optimization, the STDRIVE601 guarantees robustness when negative voltage spikes exceed 100V, and responds to logic inputs with an industry-leading 85ns. Delay matching of the high- and low-side units eliminates cycle distortion and ensures high-frequency operation. Interlocking and dead-time insertion also prevent cross-conduction under unknown conditions.
Smart shutdown circuitry ensures effective overcurrent protection, and high-speed protection shuts down the gate driver in as little as 360ns after an overload or short circuit is detected. Designers can set and adjust the protection turn-off time by changing the value of the external capacitor without affecting the turn-off response time of the chip. The chip also provides an active-low fault indication pin.
ST also provides the EVALSTDRIVE601 evaluation board to help users explore the STDRIVE601’s capabilities and quickly get up and running with their first prototypes.
negative pressure phenomenon
Negative voltage spikes in the output of a half-bridge are very common in power applications, especially when space or mechanical constraints prevent optimization of the PCB layout. Negative voltage spikes can cause undesirable phenomena such as overcharging of the bootstrap capacitor and malfunctioning of the output side when the device is not robust enough.
In the half-bridge topology, especially when driving a large inductive load, the output of the power half-bridge is prone to negative pressure, which is manifested as an initial dynamic spike and subsequent static negative pressure (as shown in Figure 1-b). This phenomenon occurs when the bridge arm is hard-switched to a low level output and the load current is output from the bridge arm to the load. When the high-side switch is closed, the inductive load element attempts to maintain a constant output current. The output voltage gradually decreases and when it drops to the “ground” level, current begins to freewheel through the low-side freewheeling diode, which conducts forward. The dynamic negative pressure is mainly due to the high dI/dt caused by the high dI/dt caused by the parasitic inductance on the PCB board in series with the freewheeling diode of the low-side current path of the half-bridge. In addition, the dynamic negative voltage is also related to the forward spike voltage of the low-side freewheeling diode (which switches from the high-voltage reverse state to the forward conducting state for a short time) and the parasitic inductance of the shunt resistor.
The static negative voltage is mainly composed of the voltage drop of the sampling resistor (if any) and the forward voltage drop of the freewheeling diode (as shown in Figure 1-a).
Figure 1 Negative voltage phenomenon of half-bridge circuit
Gate Driver Robustness
The main feature of the STDRIVE601 design is its excellent robustness to noise, disturbances and negative pressure phenomena. Thanks to the innovative level shifter architecture and ST’s advanced manufacturing process technology, the driver has excellent resistance to high negative voltage spikes and can operate normally under very steep common-mode transients.
The chip’s immunity to negative pressure spikes was tested and confirmed in a dedicated test circuit (Figure 2), designed to artificially generate negative pressure spikes much larger than those found in real-world applications.
In Figure 2, the RL load is 200 μH, 16 Ω, and in order to simulate the influence of stray inductance introduced when the PCB layout is poor, several inductances (0.19 μH, 0.45 μH, 0.82 μH) are selected to in series with the low-side IGBT.
Figure 2 Negative pressure phenomenon analysis circuit
Figure 3 shows the phenomenon when the stray inductance is 0.82 μH: the output swings from 300V to 0V, and the minimum peak value of the negative voltage peak is -127V and remains for 148ns. After several switchovers, nothing broke or malfunctioned.
Figure 3 When the stray inductance is 0.82 μH, the output of channel 1 has a negative voltage spike of -127V
The STDRIVE601 internal bootstrap diodes are implemented using rated 600V MOSFETs, which charge the bootstrap capacitors of each channel via the mains supply (VCC) when the LVG output is turned on. This avoids the use of large and expensive external high voltage diodes.
Figure 4 Comparison of STDRIVE601 bootstrap diode and traditional bootstrap diode
The built-in bootstrap circuit conducts, there is a forward bias, and there is no bias voltage present in the actual diode. The difference is shown in Figure 4, which shows the I-V (current-voltage) transfer curves of the STDRIVE601 bootstrap diode and a conventional bootstrap diode. For a given current, this feature is advantageous in terms of residual voltage drop, and can also charge the bootstrap capacitor at small voltage drops, which traditional diodes are a little less capable of.
Overcurrent intelligent shutdown protection
The STDRIVE601 has a built-in comparator that is fault protected by a Smart Shutdown (SmartSD) circuit.
The SmartSD circuit shuts down the gate driver during overload or overcurrent with a delay of only 360ns between fault detection and actual output shutdown. The protection intervention time is independent of the disable time after a fault, and the protection response is twice as fast as other gate drivers on the market. This allows the designer to increase the disable time of the output after a fault event to a very large value without increasing the internal protection delay time. The disable time depends on the value of the external capacitor COD and the value of the optional pull-up resistor connected to the OD pin (see Figure 5).
The comparator for smart shutdown has an internal reference voltage VREF connected to the inverting input and the non-inverting input is connected to pin CIN. The CIN pin of the comparator can be connected to an external shunt resistor for simple and fast overcurrent protection. The comparator output signal is filtered and input to the SmartSD logic unit, and the filtering time is a fixed time tFCIN (about 300ns).
The VREF threshold is typically 460 mV and the comparator input (CIN) hysteresis is approximately 70 mV. When the pulsed voltage on the CIN pin is higher than VREF, the SmartSD logic is triggered and immediately turns the driver output low (OFF). At the same time, the fault pin (FAULT) is forced low to indicate the event (eg input to the microcontroller) and OD begins to discharge the external capacitor COD to set the output disable time for the fault event. Once the output disable time has expired, the FAULT pin will release and the driver output will re-follow the input pin.
The total disable time consists of the following two components:
・ OD unlock time (t1 in Figure 5), that is, the time when the capacitor COD is discharged to the VSSDl threshold. Discharge begins immediately when the SmartSD comparator is triggered.
・ OD restart time (t2 in Figure 5), which is the time for the capacitor COD to recharge to the VSSDh threshold. When the voltage on the OD reaches VSSDl, the fault state is cleared (CIN < VREF - CINhyst), the internal MOSFET of the OD is turned off, and the COD is recharged at this time. This time is the main component of the disable time.
When OD is not pulled up externally, the discharge time constant of the external capacitor COD depends on the characteristics of COD and the internal MOSFET (as shown in the following equation (1)), and the restart time depends on the internal current source IOD and the capacitor COD (the following equation (2)) shown)
is the OD floating voltage.
When OD is connected to VCC via an external pull-up resistor ROD_ext, the discharge time of OD depends on the external network ROD_ext, COD and the resistance RON_OD of the internal MOSFET (as shown in equation (3) below), and the restart time depends on the current flowing through ROD_ext (see below). shown in equation (4)).
Figure 5 Smart Shutdown Timing Diagram
The figure below shows an example of the operation of the Smart Shutdown function when two different capacitors are connected to the OD pin. The trigger pulse on the CIN pin is 500ns wide, 1V peak-to-peak, and an internal current source (IOD) charges the external capacitor.
Figure 6 COD = 2.2 μF in the left picture, COD = 330 nF in the right picture
Other functions and features
STDRIVE601 has fast and accurate propagation delay. The high- and low-side drivers have a delay of 85ns from input inversion to output turn-on or turn-off, and the matching time is less than 30ns and its typical value is 0ns.
An undervoltage lockout (UVLO) mechanism monitors the output for changes in the driver supply voltage and shuts down the output when that voltage falls below a preset threshold. This protection prevents the driver from driving the power tube when the supply voltage is low (which would result in excessive conduction losses or even damage the power tube).
The UVLO threshold has hysteresis and a built-in filter prevents noise on the supply voltage from introducing unwanted motion. All 6 drivers of STDRIVE601 are protected by UVLO mechanism.
Figure 7 UVLO mechanism on VCC supply
Three-phase motors are rapidly replacing simple single-phase and brushed motors due to their many advantages. The ease of use, availability and economy of three-phase drivers such as the three-phase 600V monolithic gate driver STDRIVE601 are the main reasons for this development. STDRIVE601 offers robustness, simplicity and cost savings while ensuring the system is protected and providing safety features.
The Links: 6DI30B-050 PG640400RA4-3